1. Field of the Invention
The present invention relates to a memory device using a semiconductor.
2. Description of the Related Art
Terms used in this specification will be briefly explained. First, when one of a source and a drain of a transistor is called a drain, the other is called a source in this specification. That is, they are not distinguished depending on the potential level. Therefore, a portion called a source in this specification can be alternatively referred to as a drain.
In this specification, the term “connection” means the state where effective direct current (DC) can be supplied or can be transmitted even if the state is temporary. Therefore, a state of connection means not only a state of direct connection but also a state of indirect connection through a circuit element such as a wiring, or a resistor, in which DC can be supplied or transmitted. Note that it does not matter whether or not a circuit is designed to be actually supplied with DC.
For example, in the case where a switching element is provided between two nodes, DC can be conditionally supplied (i.e., DC can be supplied only when the switching element is in an on state); therefore, in this case, the nodes are connected to each other. On the other hand, in the case where only a capacitor is provided between two nodes, effective DC cannot be supplied through the capacitor; therefore, in this case, the nodes are not connected to each other.
Similarly, in the case where only a diode is provided between two nodes, DC can be supplied when the potential of either node is higher; therefore, in this case, the nodes are connected to each other. In that case, even when a potential at which current does not flow is applied to the two nodes in circuit design (in this case, current does not flow between the two nodes through the diode), the two nodes are connected in this specification.
For example, when a nodeA is connected to a source of a transistor and a nodeB is connected to a drain of the transistor, DC can flow between the nodeA and the nodeB depending on the gate potential is appropriate; therefore, in this case, the nodeA and the nodeB are connected.
On the other hand, when the nodeA is connected to the source of the transistor and a nodeC is connected to a gate of the transistor, effective DC cannot flow between the nodeA and the nodeC regardless of the potentials of the source, the drain, and the gate of the transistor; therefore, in this case, the nodeA and the nodeC are not connected.
In the above description, “effective DC” means current except unintended currents such as leakage current. Note that the value of effective DC is not defined by its level (absolute value) but varies depending on circuits in some cases. In other words, a low current of 1 pA can be effective current in a circuit and in another circuit, a higher current of 1 μA is not regarded as effective current in some cases.
Needless to say, in one circuit having an input and an output (e.g., inverter), the input and the output are not necessarily connected in the circuit. For example, in an inverter, an input and an output are not connected.
Further, even when the term “connect” is used in this specification, there is a case in which a corresponding physical connecting portion is not clear and a wiring is only extended in an actual circuit. For example, in an insulated-gate field-effect transistor (hereinafter simply referred to as a transistor) circuit, there is a case in which one wiring serves as gates of a plurality of transistors. In that case, one wiring which branches into gates may be illustrated in a circuit diagram. Even in such a case, the expression “a wiring is connected to a gate” may be used in this specification.
In this specification, in the case where an element in a specific row, column, or location in a matrix is described, the element is denoted by reference letters with a symbol like “a first selection transistor STr1_n_m”, “a bit line BL_m”, or “a sub bit line SBL_n_m”. Note that n and m are numbers showing a row, column, or location. When one element has a function relating to a plurality of rows or columns, the element can be denoted by “an amplifier circuit AMP_n/n+1_m”, for example.
However, an element is for example denoted by “a first selection transistor STr1”, “a bit line BL”, or “a sub bit line SBL” or simply denoted by “a first selection transistor”, “a bit line”, or “a sub bit line” in some cases, particularly in the case where a row, column, or location does not specified, where a plurality of elements are correctively denoted, or where the location is obvious.
DRAM whose memory cell includes one transistor and one capacitor can be highly integrated, has no limit of write cycles in theory, and can perform write and read at relatively high speed; thus, such DRAM is used in many kinds of electronic appliances. DRAM stores data by accumulating electric charges in a capacitor of each memory cell, and reads the data by releasing the electric charges.
A capacitor in miniaturized DRAM is formed to have a trench with a depth of as much as several micrometers and/or a protrusion with a height of as much as several micrometers, which increases difficulties in processing. Enhancement of productivity requires the capacitor to have a shape that can be easily processed. However, for that purpose, a reduction in capacitance is required, which causes the following problems, for example.
One problem caused by a lower capacitance of the capacitor is that intervals between refresh operations are shorten, which results in defective DRAM. For example, assuming that the capacitance of the capacitor is 1 fF, which is one thirtieth of conventional capacitance, the frequency of refresh operations needs to be 30 times as high as the conventional frequency of refresh operations, in which case not only smooth write or read of data is hampered but also more power is consumed.
At the time of data write in DRAM, including at the time of refresh operations, much of current flowing in a bit line is used for charging and discharging of capacitance of the bit line (including parasitic capacitance formed between a bit line and another wiring or the like) in addition to for charging of a capacitor of a memory cell. In the present situation, current ten times or more as high as current needed for charging and discharging of the capacitor of the memory cell is used for charging and discharging of the capacitance of the bit line.
Needless to say, charging and discharging of capacitance of the bit line is a phenomenon not related to data retention, and performing refresh operation leads to an increase in power consumption. Accordingly, an increase in frequency of refresh operations is not preferable because the increase leads to higher power consumption. In other words, a reduction in frequency of refresh operations is highly effective in a reduction in power consumption.
Another problem is an increase in read error. When data is read from DRAM, a slight change in potential of a bit line is amplified. The change is generated by discharging electric charges, which are accumulated in a capacitor, to the bit line.
Parasitic capacitance is between a bit line and a wiring intersecting therewith or the adjacent bit line, and is usually much higher than the capacitance of a capacitor. An extremely high capacitance of the bit line leads to extremely slight change in potential of the bit line, which is the change generated when the electric charges that are accumulated in the capacitor are discharged to the bit line; as a result, an error occurs in amplifying the change in the potential. Accordingly, the capacitance of the capacitor is desirably 10% or higher of the capacitance of the bit line.
As for the first problem, it is found that for example, the use of a semiconductor with an extremely high off resistance can markedly reduce leakage from the capacitor (see Patent Document 2). In addition, it is known that an extremely thin silicon film has off resistance higher than normal silicon by about three orders of magnitude because of the quantum effect (see Patent Document 3).
As for the second problem, a method as disclosed in Patent Document 1 is suggested in which the capacitance of the capacitor is reduced by providing a sub bit line that has a lower capacitance than the bit line and is connected to the bit line, and by connecting a sense amplifier of a flip-flop circuit type to the sub bit line. However, although the semiconductor memory device disclosed in Patent Document 1 can have a folded bit line structure, the semiconductor memory device cannot have an open bit line structure that is more highly integrated.
The sense amplifier of a flip-flop circuit type is apt to fail to work properly when the capacitance of the sub bit line is low. In general, the potential of an object with a low capacitance greatly changes because of an influence of noise. Conventional DRAM has a capacitance of bit line of several hundred femtofarads; however, based on the simplest assumption, when the capacitance of sub bit line is several femtofarads, a change in potential due to noise is increased hundredfold.
In the sense amplifier of a flip-flop circuit type, a slight potential difference of about 0.1 V is amplified in an early stage of amplification. At this time, when a change in potential other than signals becomes 0.1 V or higher, an error occurs. For example, assuming that a change in potential due to noise at an arbitrary level is 1 mV when the capacitance of the bit line is several hundred femtofarads, an error hardly occurs in a process of amplification. However, when the capacitance of the bit line (or the sub bit lines) is several femtofarads, a change in potential due to noise that is at the same level as the above; as a result, an error is apt to occur in the process of amplification.
In other words, in the semiconductor memory device disclosed in Patent Document 1, a read error is apt to occur when the capacitance of the sub bit line is greatly reduced. In the semiconductor memory device disclosed in Patent Document 1, an extremely high off resistance of a transistor is not expected and the capacitance of the sub bit line is expected to be several hundred femtofarads or higher; therefore, Patent Document 1 does not disclose any solution against the case where the capacitance of the sub bit line is several ten femtofarads or lower, for example.
In addition, in order that a potential difference of as slight as 0.1 V be amplified in such a manner, variations between threshold values of the transistors used for the sense amplifier of a flip-flop circuit type are required to be small. For example, when respective two n-channel transistors that are included in a flip-flop circuit have threshold values of +0.35 V and +0.45 V, these n-channel transistors are concurrently turned on in some cases in the process of amplification, which results in failure in data reading.
In general, a variation between the threshold values of transistors used in a flip-flop circuit is required to be less than half, preferably less than 30%, of a potential difference between bit lines in the early stage of amplification (in the above case, 0.1 V). In the above case, a variation between the threshold values of the transistors is 50 mV and a potential difference between the bit lines in the early stage of the amplification is 0.1 V; therefore, an error is apt to occur in the amplification.
Variations between the threshold values of the transistors are classified into three types: variations between lots (variations between substrates), variations between chips (variations in characteristics of chips obtained from a substrate), and variations between adjacent transistors. Variations between lots depend on difference in process condition, film thickness, or line width between lots. Variations between chips are attributed to variations in dose, film thickness, or line width in the substrate. Any of these variations is microscopic and a variation in threshold value due to these factors can be compensated by a substrate bias or the like so as to obtain needed threshold values.
On the other hand, variations between adjacent transistors mainly depend on statistical fluctuation of dopant concentration (see Non Patent Document 1). Thus, the smaller the transistor becomes, the larger the variation becomes. In other words, miniaturization of a transistor for highly integrated DRAM results in operational instability of the sense amplifier of a flip-flop circuit type.